1. Field of the Invention
This invention relates in general to microprocessors, and more particularly, to microprocessor architectures and methods for speculatively translating logical register addresses to physical addresses in an out-of-order processor having register windows.
2. Relevant Background
Modern designs of computer processors (also called microprocessors) provide registers for storing data or for providing status or control information regarding the state of the processor. With respect to data registers for storing program data during execution within the processor, a variety of register organization structures exist. One way to organize registers within a processor is to use a register windowing technique to access a plurality of registers in a register file. With register windowing, a register window has a predetermined number of contiguous registers, and the window can be moved linearly within the register file. At any one time, the register window permits program access to a subset of the total number of registers in the register file. Control registers are also associated with the register windows so that a program can manipulate the position of the window within the register file and monitor the status of the window.
For example, in the specification for a scaleable processor architecture, SPARC-V9, the general purpose registers for storing and manipulating data are arranged in register sets accessible through register windows, each register window having 32 registers. A particular processor can have multiple register sets ranging from three register sets to 32 register sets. Individual registers are addressable using a five-bit address in conjunction with a current window pointer (CWP). The register window is movable within the register sets such that a program can logically address multiple physical registers in the register sets by simply tracking a logical register name or specifier (i.e., r3! or r28!) and the current window pointer.
The five-bit register addresses encoded in an instruction word specify the instruction's source registers and the destination register. These register specifiers are logical addresses that index registers within the current register window. Because the register window is movable within the larger register file, the physical address of each register specified by a instruction will depend on the location of the current register window within the register file.
In a processor executing instructions speculatively or out-of-order, it is useful to track the physical addresses of the registers logically specified by an instruction. For instance, instruction dependency checking requires that instructions referencing the same physical register are detected so that these instructions can be executed in the proper order to eliminate the dependency.
Further, if instructions are speculatively processed within the processor, handling an instruction which is down the wrong path or mispredicted branch which may affect the position of the register window is problematic.
What is needed is a processor and method for speculatively translating logical register addresses to physical addresses accounting for the expected position of the register window within the register file.